Virtual Platform Parallel performance Evaluation

Commonly, embedded system performance is evaluated in advance through slow Instruction Set Simulators. A recent technology like binary-translation provides a faster alternative, capable to provide instruction accurate figures and model low-level details, which allows cross-development on top of the virtual platforms relying on this technology. However, early evaluations for design space esploration come before deciding the platform architecture (how many and which many processors, which interconnect, the memory hierchy and configuration, etc) and before targeting the code (what has to be executed on one processor or another, what to move to one accelerator or to HW). All those decisions compose a potentially hughe design space which demands even faster assessement speed. VIPPE relies on a cutting-edge technology called parallelized native simulation. Native simulation is a technology capable to outperform binary translation in simulation speed and to get yet estimates on time, energy and power sufficiently accurate for enabling design decisions. Moreover, VIPPE enables easy and flexible creation of platform models, getting rid from SW cross-development details, and the possibility to connect the VIPPE model to an exploration tool for an automated DSE environment. Moreover, parallelized native simulation enables VIPPE to exploit the underling parallelism of current host development platfoms.